PLL performance comparison with application to spread spectrum clock generator design

Ming Ta Hsieh, Jim Welch, Gerald E. Sobelman

Research output: Contribution to journalArticle

10 Scopus citations

Abstract

This paper presents performance, power and area comparisons of LC vs. Ring VCO-based PLL designs in order to determine the best option for high-speed spread spectrum clock generator (SSCG) designs. Analytical performance, power and area comparisons of LC versus Ring VCO-based PLL designs demonstrate that a Ring VCO can be used to meet the requirements of SATA and SAS applications at rates up to 6 Gbps. The designed SSCG operating frequency range is 2-4.25 GHz with RMS RJ jitter <1.3 and <1.5 pS for non-SSC and SSC modes, respectively, at 3 GHz. The measured EMI reduction is 18 and 21 dB for 2,300 and 4,600 ppm SSC, respectively, also at 3 GHz.

Original languageEnglish (US)
Pages (from-to)197-216
Number of pages20
JournalAnalog Integrated Circuits and Signal Processing
Volume63
Issue number2
DOIs
StatePublished - May 1 2010

Keywords

  • Digital CMOS process
  • EMI
  • LC VCO
  • Oscillator
  • Phase interpolator
  • Phase locked loop (PLL)
  • Ring VCO
  • Spread spectrum clocking (SSC)

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