Pipelined parallel FFT architectures via folding transformation

Manohar Ayinala, Michael Brown, Keshab K Parhi

Research output: Contribution to journalArticle

117 Scopus citations

Abstract

This paper presents a novel approach to develop parallel pipelined architectures for the fast Fourier transform (FFT). A formal procedure for designing FFT architectures using folding transformation and register minimization techniques is proposed. Novel parallel-pipelined architectures for the computation of complex and real valued fast Fourier transform are derived. For complex valued Fourier transform (CFFT), the proposed architecture takes advantage of under utilized hardware in the serial architecture to derive L-parallel architectures without increasing the hardware complexity by a factor of L. The operating frequency of the proposed architecture can be decreased which in turn reduces the power consumption. Further, this paper presents new parallel-pipelined architectures for the computation of real-valued fast Fourier transform (RFFT). The proposed architectures exploit redundancy in the computation of FFT samples to reduce the hardware complexity. A comparison is drawn between the proposed designs and the previous architectures. The power consumption can be reduced up to 37% and 50% in 2-parallel CFFT and RFFT architectures, respectively. The output samples are obtained in a scrambled order in the proposed architectures. Circuits to reorder these scrambled output sequences to a desired order are presented.

Original languageEnglish (US)
Article number5776727
Pages (from-to)1068-1081
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume20
Issue number6
DOIs
StatePublished - Jan 1 2012

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Keywords

  • Fast Fourier transform (FFT)
  • Folding
  • Parallel processing
  • Pipelining
  • Radix-2
  • Radix-2
  • Real signals
  • Register minimization
  • Reordering circuit

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