TY - GEN
T1 - Pipelined parallel decision feedback decoders (PDFDS) for high speed Ethernet over copper
AU - Gu, Yongru
AU - Parhi, Keshab K.
PY - 2005
Y1 - 2005
N2 - One of the powerful yet simple algorithms to decode trellis codes as well as to combat intersymbol interference (ISI) is the parallel decision-feedback decoding algorithm. However, for high-speed applications, such as Gigabit Ethernet over copper, the implementation and design of a parallel decision-feedback decoder (PDFD) is challenging due to the long critical path in the decoder structure. Straightforward pipelined designs usually introduce significant hardware overhead. To solve these problems, in this paper, first, based on an optimized scheduling of the computations in the parallel decision-feedback decoding algorithm, a low complexity pipelined PDFD is proposed. Next, we present a retiming and reformulation technique for the decision feedback unit (DFU) in the PDFD which can remove the DFU from the critical path of the PDFD with negligible hardware overhead. Compared with similar designs in the literature, the proposed design can reduce hardware overhead by 60% while achieving similar speedup for Gigabit Ethernet systems.
AB - One of the powerful yet simple algorithms to decode trellis codes as well as to combat intersymbol interference (ISI) is the parallel decision-feedback decoding algorithm. However, for high-speed applications, such as Gigabit Ethernet over copper, the implementation and design of a parallel decision-feedback decoder (PDFD) is challenging due to the long critical path in the decoder structure. Straightforward pipelined designs usually introduce significant hardware overhead. To solve these problems, in this paper, first, based on an optimized scheduling of the computations in the parallel decision-feedback decoding algorithm, a low complexity pipelined PDFD is proposed. Next, we present a retiming and reformulation technique for the decision feedback unit (DFU) in the PDFD which can remove the DFU from the critical path of the PDFD with negligible hardware overhead. Compared with similar designs in the literature, the proposed design can reduce hardware overhead by 60% while achieving similar speedup for Gigabit Ethernet systems.
UR - https://www.scopus.com/pages/publications/33646779213
UR - https://www.scopus.com/inward/citedby.url?scp=33646779213&partnerID=8YFLogxK
U2 - 10.1109/ICASSP.2005.1416255
DO - 10.1109/ICASSP.2005.1416255
M3 - Conference contribution
AN - SCOPUS:33646779213
SN - 0780388747
SN - 9780780388741
T3 - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
SP - V121-V124
BT - 2005 IEEE ICASSP '05 - Proc. - Design and Implementation of Signal Proces.Syst.,Indust. Technol. Track,Machine Learning for Signal Proces. Education, Spec. Sessions
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '05
Y2 - 18 March 2005 through 23 March 2005
ER -