Pipelined Kalman filter architecture

Naresh R. Shanbhag, Keshab K Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Presented in this paper is a hardware-efficient pipelined Kalman filter architecture for recursive least-squares (RLS) identification. The proposed architecture is developed via the relaxed look-ahead technique. This technique results in an extremely low hardware overhead at the expense of a slightly degraded performance. The hardware overhead due to pipelining consists of only the pipelining latches and is therefore negligible. Convergence analysis and simulations indicate that the adaptation accuracy of the pipelined and serial architectures are identical. Speed-up of up to 15 is demonstrated via simulations. Finally, a folded architecture for pipelined Kalman filter is presented. This folded architecture reduces the number of computational elements by half while still achieving substantial speed-up.

Original languageEnglish (US)
Title of host publicationConference Record of the Asilomar Conference of Signals, Systems & Computers
PublisherPubl by IEEE
Pages1225-1229
Number of pages5
ISBN (Print)0818641207
StatePublished - Dec 1 1993
EventProceedings of the 27th Asilomar Conference on Signals, Systems & Computers - Pacific Grove, CA, USA
Duration: Nov 1 1993Nov 3 1993

Publication series

NameConference Record of the Asilomar Conference of Signals, Systems & Computers
Volume2
ISSN (Print)1058-6393

Other

OtherProceedings of the 27th Asilomar Conference on Signals, Systems & Computers
CityPacific Grove, CA, USA
Period11/1/9311/3/93

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  • Cite this

    Shanbhag, N. R., & Parhi, K. K. (1993). Pipelined Kalman filter architecture. In Conference Record of the Asilomar Conference of Signals, Systems & Computers (pp. 1225-1229). (Conference Record of the Asilomar Conference of Signals, Systems & Computers; Vol. 2). Publ by IEEE.