Abstract
Lattice-based cryptography is a powerful cryptographic primitive that can achieve post-quantum security. The most computational-intensive operations in the lattice-based cryptographic schemes are the polynomial multiplications over the ring, which can be accelerated by adopting the number theoretic transform (NTT) in practical applications. This paper proposes a novel hardware accelerator for the NTT algorithm for lattice-based cryptography applications, which can achieve full utilization for all the hardware components. The key ideas involve exploiting well-designed folding sets and applying the folding transformations to adapt the fast Fourier transform (FFT) multi-path delay commutator architectures and a lightweight modular multiplier.
Original language | English (US) |
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Title of host publication | Proceedings of the 2021 Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2021 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781665441858 |
DOIs | |
State | Published - 2021 |
Event | 6th Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2021 - Shanghai, China Duration: Dec 17 2021 → Dec 18 2021 |
Publication series
Name | Proceedings of the 2021 Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2021 |
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Conference
Conference | 6th Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2021 |
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Country/Territory | China |
City | Shanghai |
Period | 12/17/21 → 12/18/21 |
Bibliographical note
Funding Information:This research was supported in part by the Semiconductor Research Corporation under contract number 2020-HW-2998. 978-1-6654-4185-8/21/$31.00 ©2021 IEEE
Publisher Copyright:
© 2021 IEEE.
Keywords
- Homomorphic Encryption
- Lattice-based Cryptography
- Number theoretic transform
- Post-quantum Cryptography
- Security