Pipelined CORDIC-based cascade orthogonal IIR digital filters

Jun Ma, Keshab K Parhi, Ed F. Deprettere

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

CORDIC-based cascade orthogonal infinite-impulse response (IIR) digital filters possess desirable properties for VLSI implementations such as local connection, regularity, absence of limit cycle and overflow oscillations, and good finite word-length behavior. However, the achievable sample rate of these filters is limited, since these structures cannot be pipelined at finer levels (such as bit or multi-bit level) due to the presence of feedback loops. In this paper, we present a novel approach to design pipelined CORDIC-based cascade orthogonal IIR digital filters using the transfer function approach. We first present a systematic way to synthesize cascade orthogonal IIR digital filters using scalar lossless inverse scattering theory, and realize the filter transfer function as a cascade inter-connection of orthogonal sections where each section implements one real zero or a pair of complex conjugate zeroes of the transfer function. In this way, the filter achieves low sensitivity over the entire filter spectrum. Novel pipelining techniques for both coarse-grain and fine-grain pipelining of these filters are then proposed. In coarse-grain pipelining, we present a novel method based on retiming and orthogonal matrix decomposition techniques which can increase the maximum filter sample rate to O(1) level which is independent of the filter order. In fine-grain pipelining, we present a novel method based on constraint filter design and polyphase decomposition techniques which could increase the maximum filter sample rate to any desired level. The proposed architecture for coarse-grain pipelining consists of only Givens rotations, and the one for fine-grain pipelining consists of only Givens rotations and a few additions. Both architectures can be realized using CORDIC arithmetic-based processors. Finally, finite word-length simulations are carried out to compare the performance of different topologies.

Original languageEnglish (US)
Pages (from-to)1238-1253
Number of pages16
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume47
Issue number11
DOIs
StatePublished - Nov 2000

Bibliographical note

Funding Information:
Manuscript received June 1998; revised July 2000. This work was supported in part by the National Science Foundation under Grant MIP-9258670. This paper was recommended by Associate Editor W. Liu. J. Ma was with the Department of Electrical and Computer Engineering, University of Minnesota. He is now with Broadcom Corporation, Irvine, CA 92619 USA (e-mail: junmap@yahoo.com). K. K. Parhi is with the Department of Electrical and Computer Engineering at the University of Minnesota, Minneapolis, MN 55455 USA. E. F. Deprettere is with Leiden Institute of Advanced Computer Sciences, Leiden University, Leiden, The Netherlands. Publisher Item Identifier S 1057-7130(00)09928-6.

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