Pipelined Adaptive DFE Architectures Using Relaxed Look-Ahead

Naresh R. Shanbhag, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

28 Scopus citations


Fine-grain pipelined adaptive decision-feedback equalizer (ADFE) architectures are developed using the relaxed look-ahead technique. This technique, which is an approximation to the conventional look-ahead computation, maintains functionality of the algorithm rather than the input-output behavior. Thus, it results in substantial hardware savings as compared to either parallel processing or look-ahead techniques. Pipelining of the decision feedback loop and the adaptation loop is achieved by the use of delay relaxation and sum relaxation. Both the conventional and the predictor form of ADFE have been pipelined. Results of the convergence analysis of the proposed algorithms are also provided. The performance of the pipelined algorithms for the equalization of a magnetic recording channel is studied. It is shown that the conventional ADFE results in an SNR loss of about 0.6 dB per unit increase in the speed-up factor. The predictor form of ADFE is much more robust and results in less than 0.1 dB SNR loss per unit increase in the speed-up factor. Speed-ups of up to 8 and 45 have been demonstrated for the conventional and predictor forms of ADFE.

Original languageEnglish (US)
Pages (from-to)1368-1385
Number of pages18
JournalIEEE Transactions on Signal Processing
Issue number6
StatePublished - Jun 1995

Bibliographical note

Funding Information:
Manuscript received September 8, 1993; revised November 10, 1994. This research was supported by the Army Research Office under Contract DAAL-90-G-0063. The associate editor coordinating the review of this paper and approving it for publication was Dr. J. Zeider. N. R. Shanbhag is with AT&T Bell Laboratories in Murray Hill, NJ 07974 USA. K. K. Parhi is with the Department of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455 USA. IEEE Log Number 941 1201.

Funding Information:
B. Tech. (Hon.) degree from the Indian Institute of Technology, Kharagpur, in 1982, the M.S.E.E. de-gree from the University of Pennsylvania, Philadel-phia, in 1984, and the Ph.D. degree from the Uni-versity of California, Berkeley, in 1988. He has been with the University of Minnesota since 1988, where he is currently a Professor of Electrical Engineering. He has also held short-term positions in several industries. His research in-terests include concurrent algorithm and architecture designs for communications, signal and image processing systems, digital integrated circuits, VLSI digital filters, computer arithmetic, high-level DSP synthesis, and multiprocessor prototyping and task scheduling for programmable software systems. He has published over 130 papers in these areas. Dr. Parhi received the 1994 Darlington and the 1993 Guillemin-Cauer Best Paper awards from the IEEE Circuits and Systems Society, the 1991 Best Paper award from the IEEE Signal Processing Society, the 1991 Browder Thompson prize paper award from the IEEE, the 1992 Young Investigator Award of the National Science Foundation, the 1992-1994 McKnight-Land Grant professorship of the University of Minnesota, and the 1987 Eliahu Jury Award for Excellence in Systems Research at the University of California, Berkeley. He is a former Associate Editor of Image Processing and VLSI Applications in the IEEE TRANSACTIOONN SC IRCUITASN D SYSTEMSan d is a current Associate Editor of the IEEE TRANSACTIOONNS S IGNAPL ROCESS[NG, an editor of the Journal of VLSI Signal Processing, and is a member of Eta Kappa Nu.


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