TY - JOUR
T1 - PIMBALL
T2 - Binary neural networks in spintronic memory
AU - Resch, Salonik
AU - Khatamifard, S. Karen
AU - Chowdhury, Zamshed Iqbal
AU - Zabihi, Masoud
AU - Zhao, Zhengyang
AU - Wang, Jian Ping
AU - Sapatnekar, Sachin S.
AU - Karpuzcu, Ulya R.
N1 - Publisher Copyright:
© 2019 Association for Computing Machinery.
PY - 2019/10
Y1 - 2019/10
N2 - Neural networks span a wide range of applications of industrial and commercial significance. Binary neural networks (BNN) are particularly effective in trading accuracy for performance, energy efficiency, or hardware/ software complexity. Here, we introduce a spintronic, re-configurable in-memory BNN accelerator, PIMBALL: Processing In Memory BNN AcceL(L)erator, which allows for massively parallel and energy efficient computation. PIMBALL is capable of being used as a standard spintronic memory (STT-MRAM) array and a computational substrate simultaneously. We evaluate PIMBALL using multiple image classifiers and a genomics kernel. Our simulation results show that PIMBALL is more energy efficient than alternative CPU-, GPU-, and FPGA-based implementations while delivering higher throughput.
AB - Neural networks span a wide range of applications of industrial and commercial significance. Binary neural networks (BNN) are particularly effective in trading accuracy for performance, energy efficiency, or hardware/ software complexity. Here, we introduce a spintronic, re-configurable in-memory BNN accelerator, PIMBALL: Processing In Memory BNN AcceL(L)erator, which allows for massively parallel and energy efficient computation. PIMBALL is capable of being used as a standard spintronic memory (STT-MRAM) array and a computational substrate simultaneously. We evaluate PIMBALL using multiple image classifiers and a genomics kernel. Our simulation results show that PIMBALL is more energy efficient than alternative CPU-, GPU-, and FPGA-based implementations while delivering higher throughput.
KW - Binary neural networks
KW - Computational random access memory
KW - Non-volatile memory
KW - Processing in memory
UR - http://www.scopus.com/inward/record.url?scp=85073722481&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85073722481&partnerID=8YFLogxK
U2 - 10.1145/3357250
DO - 10.1145/3357250
M3 - Article
AN - SCOPUS:85073722481
SN - 1544-3566
VL - 16
JO - ACM Transactions on Architecture and Code Optimization
JF - ACM Transactions on Architecture and Code Optimization
IS - 4
M1 - A41
ER -