Performance study of a concurrent multithreaded processor

Jenn Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen Chung Yew

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations


The performance of a concurrent multithreaded architectural model, called superthreading, is studied in this paper. It tries to integrate optimizing compilation techniques and run-time hardware support to exploit both thread-level and instruction-level parallelism, as opposed to exploiting only instruction-level parallelism in existing superscalars. The superthreaded architecture uses a thread pipelining execution model to enhance the overlapping between threads, and to facilitate data dependence enforcement between threads through compiler-directed, hardware-supported, thread-level control speculation and run-time data dependence checking. We also evaluate the performance of the superthreaded processor through a detailed trace-driven simulator. Our results show that the superthreaded execution model can obtain good performance by exploiting both thread-level and instruction-level parallelism in programs. We also study the design parameters of its main system components, such as the size of the memory buffer, the bandwidth requirement of the communication links between thread processing units, and the bandwidth requirement of the shared data cache.

Original languageEnglish (US)
Title of host publicationIEEE High-Performance Computer Architecture Symposium Proceedings
PublisherInstitute of Electrical and Electronics Engineers Computer Society
Number of pages12
StatePublished - Jan 1 1998
EventProceedings of the 1998 4th International Symposium on High-Performance Computer Architecture, HPCA - Las Vegas, NV, USA
Duration: Jan 31 1998Feb 4 1998


OtherProceedings of the 1998 4th International Symposium on High-Performance Computer Architecture, HPCA
CityLas Vegas, NV, USA


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