Performance-scalable array architectures for modular multiplication

William L. Freking, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

Modular multiplication is a fundamental operation in numerous public-key cryptosystems including the RSA method. Increasing popularity of internet e-commerce and other security applications translate into a demand for a scalable performance hardware design framework. Previous scalable hardware methodologies either were not systolic and thus involved performance-degrading, full-word-length broadcasts or were not scalable beyond linear array size. In this paper, these limitations are overcome with the introduction of three classes of scalable-performance modular multiplication architectures based on systolic arrays. Very high clock rates are feasible, since the cells composing the architectures are of bit-level complexity. Architectural methods based on both binary and high-radix modular multiplication are derived. All techniques are constructed to allow additional flexibility for the impact of interconnect delay within the design environment.

Original languageEnglish (US)
Pages (from-to)101-116
Number of pages16
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Volume31
Issue number2
DOIs
StatePublished - Jun 1 2002

Keywords

  • High-radix arithmetic implementation
  • Modular multipliers
  • Pipelined architectures
  • Systolic computation

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