Performance-scalable array architectures for modular multiplication

William L. Freking, Keshab K Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

Modular multiplication is a fundamental operation in numerous public-key cryptosystems including the RSA method. Increasing popularity of internet e-commerce and other security applications translate into a demand for a scalable performance hardware design framework. Previous scalable hardware methodologies either were not systolic and thus involved performance-degrading, full-world-length broadcasts or were not scalable beyond linear array size. In this paper, these limitations are overcome with the introduction of three scalable-performance modular multiplication architectures based on systolic arrays. Very high clock rates are feasible, since the cells composing the architectures are of bit-level complexity. Architectural methods based on both binary and high-radix modular multiplication are derived. All techniques are constructed to allow additional flexibility for the impact of interconnect delay within the design environment.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
PublisherIEEE
Pages149-160
Number of pages12
StatePublished - Jan 1 2000
Event2000 IEEE International Conference on Application-Specific Systems, Architectures, and Processors - Boston, MA, USA
Duration: Jul 10 2000Jul 12 2000

Other

Other2000 IEEE International Conference on Application-Specific Systems, Architectures, and Processors
CityBoston, MA, USA
Period7/10/007/12/00

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