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Performance optimization by gate sizing and path sensitization
Juho Kim,
David H C Du
Computer Science and Engineering
Research output
:
Contribution to journal
›
Article
›
peer-review
4
Scopus citations
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Keyphrases
Performance Optimization
100%
Path Sensitization
100%
Gate Sizing
100%
Clock Period
100%
Selection Strategy
66%
Shortest Path
66%
Longest Path
66%
Resizing
66%
Combinational Circuits
33%
Benchmark Circuits
33%
Input Vector
33%
Circuit Model
33%
Gate Resizing
33%
Computer Science
Performance Optimization
100%
Clock Period
100%
Selection Method
66%
Critical Path
33%
Benchmark Circuit
33%
Combinational Circuit
33%
Experimental Result
33%
Engineering
Clock Period
100%
Selection Method
66%
Experimental Result
33%
Circuit Model
33%
Input Vector
33%
Combinatorial Circuits
33%
Critical Path
33%