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Performance modeling for CNN inference accelerators on FPGA
Yufei Ma
,
Yu Cao
, Sarma Vrudhula
, Jae Sun Seo
Research output
:
Contribution to journal
›
Article
›
peer-review
55
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Scopus citations
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Keyphrases
Array-based
66%
Communication Access
33%
Computational Resources
33%
Convolutional Neural Network
100%
Convolutional Neural Network Algorithm
33%
Data Communication
33%
Data Memory
33%
Design Decisions
33%
Design Parameters
33%
Design Phase
33%
Energy Efficiency
33%
External Memory
33%
Field Programmable Gate Array
100%
Field Programmable Gate Array Implementation
33%
High Energy
33%
High Performance
33%
Implementation Process
33%
Large Design Spaces
33%
Memory Access
33%
Model Evaluation
66%
Neural Network Accelerator
100%
On-board Test
33%
On-chip Buffer
33%
Parallelization
33%
Performance Bottleneck
33%
Performance Efficiency
33%
Performance Modeling
100%
Performance-based Design
33%
Resource Utilization
33%
Computer Science
Artificial Neural Network
20%
Convolutional Neural Network
100%
Data Communication
20%
Design Parameter
20%
Design Phase
20%
Energy Efficiency
20%
External Memory
20%
Field Programmable Gate Arrays
100%
Implementation Phase
20%
Memory Access
20%
Network Inference
100%
Parallelism
20%
Performance Bottleneck
20%
Performance Model
100%
Resource Utilisation
20%
Physics
Artificial Neural Network
33%
Convolutional Neural Network
100%
Energy Efficiency
33%