Performance evaluation and optimal design for FPGA-based digit-serial DSP functions

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19 Scopus citations

Abstract

As field programmable gate array (FPGA) technology has steadily improved, FPGAs are now viable alternatives to other technology implementations for high-speed classes of digital signal processing (DSP) applications. Digit-serial DSP architectures have been effective implementation method for FPGAs. In this work, a method of implementing digit-serial DSP architectures on FPGAs is presented, and their performance is evaluated with the objective of finding and developing the most efficient digit-serial DSP architectures on FPGAs. This paper discusses area costs and operational delays of the various digit-serial DSP functions and presents the area/delay models on Xilinx XC4000-series FPGAs. These area/delay models can make predictions of performance and hardware resource utilization before a lengthy layout and synthesis process is undertaken. The results show that the area/delay models proposed here are valid and the digit-serial DSP designs are promising candidates for efficient FPGA implementations.

Original languageEnglish (US)
Pages (from-to)357-377
Number of pages21
JournalComputers and Electrical Engineering
Volume29
Issue number2
DOIs
StatePublished - Mar 2003

Bibliographical note

Funding Information:
This research was supported by Defense Advanced Research Project Agency under contract number DA/DABT63-96-C-0050. We would like to thank Keshab Parhi for valuable conversations.

Copyright:
Copyright 2004 Elsevier Science B.V., Amsterdam. All rights reserved.

Keywords

  • Adder
  • Arithmetic
  • Digit serial
  • Digital signal processing
  • FIR filter
  • Field programmable gate array
  • Multiplier

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