Performance driven global routing through gradual refinement

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Abstract

We propose a method for VLSI interconnect global routing that can optimize routing congestion, delay and number of bends, which are often competing objectives. Routing flexibilities under timing constraints are obtained and exploited to reduce congestion subject to timing constraints. The wire routes are determined through gradual refinement according to probabilistic estimation on congestions so that the congestion is minimized while the number of bends on wires are limited. The experiments on both random generated circuits and benchmark circuits confirm the effectiveness of this method.

Original languageEnglish (US)
Article number70
Pages (from-to)481-483
Number of pages3
JournalProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
DOIs
StatePublished - 2001

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