TY - JOUR
T1 - Performance characterization and majority gate design for MESO-based circuits
AU - Zhaoxin, Liang
AU - Mankalale, Meghna G.
AU - Hu, Jiaxi
AU - Zhao, Zhengyang
AU - Wang, Jian Ping
AU - Sapatnekar, Sachin S.
N1 - Publisher Copyright:
© 2018 IEEE.
Copyright:
Copyright 2019 Elsevier B.V., All rights reserved.
PY - 2018
Y1 - 2018
N2 - Magnetoelectric spin-orbit (MESO) logic is a promising spin-based post-CMOS logic computation paradigm. This paper explores the application of the basic MESO device concept to more complex logic structures. A simulation framework is first developed to facilitate the performance evaluation of MESO-based circuits. Based on the analysis, it is seen that inadvertent logic errors may potentially be introduced in cascaded MESO stages due to sneak paths, and solutions for overcoming this problem with a short pulse and two-phase evaluation are discussed. Next, the generalization of the MESO inverter structure to majority logic gates is shown. Two implementations, based on different physical mechanisms, are presented and a relative analysis of their speed and power characteristics is provided. 2018 IEEE.
AB - Magnetoelectric spin-orbit (MESO) logic is a promising spin-based post-CMOS logic computation paradigm. This paper explores the application of the basic MESO device concept to more complex logic structures. A simulation framework is first developed to facilitate the performance evaluation of MESO-based circuits. Based on the analysis, it is seen that inadvertent logic errors may potentially be introduced in cascaded MESO stages due to sneak paths, and solutions for overcoming this problem with a short pulse and two-phase evaluation are discussed. Next, the generalization of the MESO inverter structure to majority logic gates is shown. Two implementations, based on different physical mechanisms, are presented and a relative analysis of their speed and power characteristics is provided. 2018 IEEE.
KW - Inverse spin-orbit coupling (ISOC)
KW - Magnetoelectric (ME) coupling
KW - Majority gate
KW - Simulation
KW - Spintronics
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U2 - 10.1109/JXCDC.2018.2874805
DO - 10.1109/JXCDC.2018.2874805
M3 - Article
AN - SCOPUS:85065899541
SN - 2329-9231
VL - 4
SP - 51
EP - 59
JO - IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
JF - IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
IS - 2
M1 - 8485738
ER -