## Abstract

This paper analyzes the performance and scalability of an iteration of the preconditioned conjugate gradient algorithm on parallel architectures with a variety of interconnection networks, such as the mesh, the hypercube, and that of the CM-5™ 1 parallel computer. It is shown that for block-tridiagonal matrices resulting from two-dimensional finite difference grids, the communication overhead due to vector inner products dominates the communication overheads of the remainder of the computation on a large number of processors. However, with a suitable mapping, the parallel formulation of a PCG iteration is highly scalable for such matrices on a machine like the CM-5 whose fast control network practically eliminates the overheads due to inner product computation. The use of the truncated Incomplete Cholesky (IC) preconditioner can lead to further improvement in scalability on the CM-5 by a constant factor. As a result, a parallel formulation of the PCG algorithm with IC preconditioner may execute faster than that with a simple diagonal preconditioner even if the latter runs faster in a serial implementation. For the matrices resulting from three-dimensional finite difference grids, the scalability is quite good on a hypercube or the CM-5, but not as good on a 2-D mesh architecture. In the case of unstructured sparse matrices with a constant number of nonzero elements in each row, the parallel formulation of the PCG iteration is unscalable on any message passing parallel architecture, unless some ordering is applied on the sparse matrix. The parallel system can be made scalable either if, after reordering, the nonzero elements of the N ×N matrix can be confined in a band whose width is O(Ny) for any y < 1, or if the number of nonzero elements per row increases as Nx for any x > 0. Scalability increases as the number of nonzero elements per row is increased and/or the width of the band containing these elements is reduced. For unstructured sparse matrices, the scalability is asymptotically the same for all architectures. Many of these analytical results are experimentally verified on the CM-5 parallel computer.

Original language | English (US) |
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Pages (from-to) | 455-469 |

Number of pages | 15 |

Journal | IEEE Transactions on Parallel and Distributed Systems |

Volume | 6 |

Issue number | 5 |

DOIs | |

State | Published - May 1995 |

### Bibliographical note

Funding Information:Manuscript received February 23, 1993; revised June I, 1994. This work was supported by IST/SDIO through the Army Research Office under Grant 28408-MA-SDI to the University of Minnesota, and by the University of Minnesota Army High Performance Computing Research Center under Contract DAAL03-89-C-0038. The authors are with the Department of Computer Science, University of Minnesota, Minneapolis, MN 55455 USA. IEEE Log Number 9409876.