Performance and Optimization of Dipole Heterostructure Field-Effect Transistor

Junping Zou, Haozhe Dong, Anand Gopinath

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

A new class of devices, the Dipole Heterostructure Field Effect Transistors (Dipole HFET’s), are proposed and have been fabricated in AlGaAs/GaAs. Doped p++ and n++ planes in the charge control AlGaAs layer form a dipole that creates a considerably larger barrier between the channel and the gate than in conventional heterostructure FET’s. This leads to a sharp reduction of the forward-biased gate current in enhancement-mode n-channel devices, a much broader transconductance peak, and a higher maximum drain current in enhancement-mode devices. The paper also outlines an analytical theory, supported by numerical modeling, the optimization of device structures for both enhancement- and depletion-mode devices. This is supported by experimental device results obtained from enhancement devices.

Original languageEnglish (US)
Pages (from-to)250-256
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume39
Issue number2
DOIs
StatePublished - Feb 1992

Bibliographical note

Funding Information:
Manuscript received November 13, 1990; revised June 14, 1991. This work was supported by the Microelectronic Information and Science Center of the University of Minnesota, the Minnesota Supercomputer Institute, and the Office of Naval Research. The review of this paper was arranged by Associate Editor M. D. Feuer. J. Zou, H. Dong, and A. Gopinath are with the Department of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455. M. Shur is with the Department of Electrical Engineering, University of Virginia, Charlottesville, VA 22903-2442, and the Minnesota Supercomputer Institute, Minneapolis, MN. IEEE Log Number 9104668.

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