Performance analysis of III-V materials in a double-gate nano-MOSFET

Kurtis D. Cantley, Yang Liu, Himadri S. Pal, Tony Low, Shaikh S. Ahmed, Mark S. Lundstrom

Research output: Contribution to journalConference articlepeer-review

33 Scopus citations


Nanoscale double-gate n-MOSFETs with silicon and III-V (GaAs and InAs) channels are studied using numerical simulation. The device structures are based on the ITRS 14nm node (year 2020), and are simulated using the program nanoMOS, which utilizes the NEGF technique for treating ballistic electron transport in the channel. The effective masses used are obtained by extraction from the full band structure using the sp3d5s* empirical tight-binding method. This process returns effective mass values for all valleys which are far more accurate than bulk values for the ultra-thin-body MOSFET. The results indicate that for digital logic applications, III-V materials offer little or no performance advantage over silicon for ballistic devices near the channel length scaling limit.

Original languageEnglish (US)
Article number4418877
Pages (from-to)113-116
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting, IEDM
StatePublished - Dec 1 2007
Event2007 IEEE International Electron Devices Meeting, IEDM - Washington, DC, United States
Duration: Dec 10 2007Dec 12 2007


Dive into the research topics of 'Performance analysis of III-V materials in a double-gate nano-MOSFET'. Together they form a unique fingerprint.

Cite this