Pathfinding for 22nm CMOS designs using Predictive Technology Models

Xia Li, Wei Zhao, Yu Cao, Zhi Zhu, Jooyoung Song, David Bang, Chi Chao Wang, Seung H. Kang, Joseph Wang, Matt Nowak, Nick Yu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations


Traditional IC scaling is becoming increasingly difficult at the 22nm node and beyond. Dealing with these challenges increase product development cycle time. For continued CMOS scaling, it is essential to start design explorations in new process nodes as early as possible. Such an effort requires having Predictive Technology Models, which bridge technological and design practices, in order to assess the performance impact of future key modules. In this paper we propose a strategy that enables simultaneous investigation of advanced process and design concepts. Based on a customized predictive methodology and silicon data at 90-45nm nodes, compact transistor and interconnect models are developed for the next generation CMOS technology. We capture the heuristic device behavior during the scaling, which helps us to gain key insights that allow us to make tradeoffs of circuit performance metrics for next technology node.

Original languageEnglish (US)
Title of host publication2009 IEEE Custom Integrated Circuits Conference, CICC '09
Number of pages4
StatePublished - 2009
Externally publishedYes
Event2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States
Duration: Sep 13 2009Sep 16 2009

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930


Other2009 IEEE Custom Integrated Circuits Conference, CICC '09
Country/TerritoryUnited States
CitySan Jose, CA


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