Path sensitization approach to area reduction

Hsi chuan Chen, Siu Wing Cheng, Yaun chung Hsu, David H.C. Du

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

We study the problem of choosing gate implementations to reduce circuit area while retaining the circuit performance. To incorporate timing analysis into area reduction, we propose to utilize the information provided by a sensitization criterion in computing the slacks of the gates. Not all sensitization criteria can be adopted in our approach. Some conditions was imposed to define a class of sensitization criteria which can guarantee that the circuit performance will be preserved. A greedy area reduction heuristic is proposed, and then an improved version of the Brand-Iyengar and the static sensitization criteria are plugged into the heuristic to obtain results for comparison.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors
Editors Anon
PublisherPubl by IEEE
Pages73-76
Number of pages4
ISBN (Print)0818642300
StatePublished - Dec 1 1993
EventProceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA
Duration: Oct 3 1993Oct 6 1993

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Other

OtherProceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors
CityCambridge, MA, USA
Period10/3/9310/6/93

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