Parallel VLSI architectures for a class of LDPC codes

Keyphrases

• Low-density Parity-check Codes 100%
• VLSI Architecture 100%
• High Performance 50%
• Hardware Complexity 50%
• Bit Error Rate 50%
• Decoder 50%
• Encoder 50%
• Code Rate 50%
• VLSI Implementation 50%
• Concatenated 50%
• Encoder-decoder Architecture 50%
• 6-bit 50%
• Block Size 50%
• Parity Check Matrix 50%
• Encoder Architecture 50%
• Bit Quantization 50%
• Generator Matrix 50%
• Parity Check 50%
• Encoder Structure 50%

Engineering

• Parity Check Code 100%
• Simulation Result 50%
• Code Rate 50%
• Hardware Complexity 50%
• Block Size 50%
• Parity Check Matrix 50%
• Generator Matrix 50%
• Bit Error Rate 50%

Computer Science

• Very large-scale integration (VLSI) architecture 100%
• low density parity check code 100%
• Parity Check Matrix 50%
• Generator Matrix 50%
• Computer Hardware 50%