Parallel turbo decoding

Yuping Zhang, Keshab K Parhi

Research output: Contribution to journalArticlepeer-review

33 Scopus citations


Turbo codes are one of the most powerful error correcting codes. The VLSI implementation of Turbo codes for higher decoding speed requires use of parallel architectures. This paper explores the design spaces of both serial and parallel MAP decoders using graphical analysis. Several existing designs are compared, and three new parallel decoding schemes are presented.

Original languageEnglish (US)
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - Sep 7 2004


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