Parallel Resonant DC Link Circuit—A Novel Zero Switching Loss Topology with Minimum Voltage Stresses

Jin He, Ned Mohan

Research output: Contribution to journalArticlepeer-review

63 Scopus citations


A parallel-resonant dc link (PRDCL) circuit topology as new approach to realizing zero switching loss dc-ac high switching frequency power conversion is presented. The proposal circuit is used as an interface between dc voltage supply and the voltage source PWM inverter to provide a short zero voltage period in the dc link of the inverter to allow zero voltage switchings to take place in the PWM inverter. Moreover, the peak voltage stress on the PWM inverter switches is limited to the dc supply voltage Vs. Another significant advantage of the proposed circuit is that the inverter can be controlled by the conventional PWM strategy. The proposed circuit has been systematically analyzed and its operation principle has been explained in detail. Design considerations and design formulas are also presented. A complete zero voltage switching dc-ac system consisting of the proposed circuit and the PWM inverter is simulated on computer.

Original languageEnglish (US)
Pages (from-to)687-694
Number of pages8
JournalIEEE Transactions on Power Electronics
Issue number4
StatePublished - Oct 1991

Bibliographical note

Funding Information:
The authors gratefully acknowledge the financial support from the University of Minnesota for Electric Energy, sponsored by the MinnesotaIWisconsin Power Suppliers group.


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