Parallel Processing Architectures for Rank Order and Stack Filters

Lori E. Lucke, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

38 Scopus citations


Many architectures have been proposed for rank order and stack filtering. To achieve additional speedup in these structures requires the use of parallel processing techniques such as pipelining and block processing. Pipelining is well understood but few block architectures have been developed for rank order and stack filtering. Block processing is essential for additional speedup when the original architecture has reached the throughput limits caused by the underlying technology. A trivial block structure simply repeats a single input, single output structure to generate a multiple input, multiple output structure. Therefore the architecture can achieve speedups equal to the number of multiple outputs or the block size. However, unlike linear filters, the rank order and stack filter outputs are calculated using comparisons. It is possible to share these comparisons within the block structure and thus substantially reduce the size of the block structure. In this paper we introduce a systematic method for applying block processing to rank order filters and stack filters. This method takes advantage of shared comparisons within the block structure to generate a block filter with shared substructures whose complexity is reduced by up to one-third compared to the original filter structure times the block size. Furthermore, block processing is important for the generation of low power designs. A block structure can trade its increased speedup for a throughput equal to the original single output architecture but with a significantly lower power requirement. The power reduction in the trivial block structures is limited by the power supply voltage. With shared substructures the size of the block structure is decreased and thus the power consumption is further reduced. In this paper we demonstrate how block structures with shared substructures allow us to continue decreasing the power consumption beyond the limit imposed by the supply voltage.

Original languageEnglish (US)
Pages (from-to)1178-1189
Number of pages12
JournalIEEE Transactions on Signal Processing
Issue number5
StatePublished - May 1994

Bibliographical note

Funding Information:
Manuscript received Maarch 24, 1992; revised July 4, 1993. The associate editor coordinating the review of this paper and approving it for publication was Prof. Ed F. Deprettere. This work was supported in part by an AT&T graduate fellowship and the Office of Naval Research under contract number N00014-9 I -J- 1008.


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