@inproceedings{a06ae5cf04114ba5b2bd726830d9e8d8,
title = "Parallel-pipelined radix-22 FFT architecture for real valued signals",
abstract = "This paper presents a novel parallel-pipelined architecture for the computation of real valued fast Fourier transform (RFFT). The proposed architecture takes advantage of the redundancy of some computations with respect to complex FFT along with low multiplicative complexity of the radix-2 2 architecture. Folding transformation is used to derive a novel parallel-pipelined architecture by exploiting the redundancy in the modified flow graph. The proposed parallel architecture requires log4N - 1 complex multipliers and N - 1 complex delay elements.",
keywords = "FFT, Folding, Parallel Processing, Pipelining, Real Signals, radix-2",
author = "Manohar Ayinala and Parhi, {Keshab K}",
year = "2010",
doi = "10.1109/ACSSC.2010.5757736",
language = "English (US)",
isbn = "9781424497218",
series = "Conference Record - Asilomar Conference on Signals, Systems and Computers",
pages = "1274--1278",
booktitle = "Conference Record of the 44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010",
note = "44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010 ; Conference date: 07-11-2010 Through 10-11-2010",
}