Parallel pipelined FFT architectures with reduced number of delays

Manohar Ayinala, Keshab K Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations


This paper presents a novel approach to design four and eight parallel pipelined fast Fourier transform (FFT) architectures using folding transformation. The approach is based on use of decimation in time algorithms which reduce the number of delay elements by 33% compared to the decimation in frequency based designs. The number of delay elements required for an N-point FFT architecture is N -4 which is comparable to that of delay feedback schemes. The number of complex adders required is only 50% of those in the delay feedback designs. The proposed approach can be extended to any radix-2 n based FFT algorithms. The proposed architectures are feed-forward designs and can be pipelined by more stages to increase the throughput. Further, a novel four parallel 128-point FFT architecture is derived using the proposed approach. It is shown that a radix- 2 4 4-parallel 128-point design requires 124 delay elements, 28 complex adders, and four full complex multipliers.

Original languageEnglish (US)
Title of host publicationGLSVLSI'12 - Proceedings of the Great Lakes Symposium on VLSI 2012
Number of pages4
StatePublished - May 22 2012
Event22nd Great Lakes Symposium on VLSI, GLSVLSI'2012 - Salt Lake City, UT, United States
Duration: May 3 2012May 4 2012

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI


Other22nd Great Lakes Symposium on VLSI, GLSVLSI'2012
Country/TerritoryUnited States
CitySalt Lake City, UT


  • Decimation-in-time (DIT)
  • Eight parallel
  • Fast fourier transform (FFT)
  • Folding
  • Four parallel
  • Radix-2


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