Parallel FFT computation with a CDMA-based network-on-chip

Daewook Kim; Manho Kim; Gerald E. Sobelman

doi:10.1109/ISCAS.2005.1464794

Parallel FFT computation with a CDMA-based network-on-chip

Daewook Kim, Manho Kim, Gerald E. Sobelman

Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

11 Scopus citations

Abstract

Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations. We present two methodologies for mapping an FFT computation onto a CDMA-based star topology network-on-chip (NoC) architecture. These implementations reduce the FFT data shuffling time and simplify the data flow between processing elements. The design has been modeled using SystemC and the simulation results provide throughput and latency performance metrics for the different mapping scenarios.

Original language	English (US)
Article number	1464794
Pages (from-to)	1138-1141
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1464794
State	Published - 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: May 23 2005 → May 26 2005

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10.1109/ISCAS.2005.1464794

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abstract = "Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations. We present two methodologies for mapping an FFT computation onto a CDMA-based star topology network-on-chip (NoC) architecture. These implementations reduce the FFT data shuffling time and simplify the data flow between processing elements. The design has been modeled using SystemC and the simulation results provide throughput and latency performance metrics for the different mapping scenarios.",

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AU - Kim, Manho

AU - Sobelman, Gerald E.

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AB - Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations. We present two methodologies for mapping an FFT computation onto a CDMA-based star topology network-on-chip (NoC) architecture. These implementations reduce the FFT data shuffling time and simplify the data flow between processing elements. The design has been modeled using SystemC and the simulation results provide throughput and latency performance metrics for the different mapping scenarios.

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JO - Proceedings - IEEE International Symposium on Circuits and Systems

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T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005

Y2 - 23 May 2005 through 26 May 2005

ER -

Parallel FFT computation with a CDMA-based network-on-chip

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