Parallel FFT computation with a CDMA-based network-on-chip

Daewook Kim, Manho Kim, Gerald E. Sobelman

Research output: Contribution to journalConference articlepeer-review

11 Scopus citations


Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations. We present two methodologies for mapping an FFT computation onto a CDMA-based star topology network-on-chip (NoC) architecture. These implementations reduce the FFT data shuffling time and simplify the data flow between processing elements. The design has been modeled using SystemC and the simulation results provide throughput and latency performance metrics for the different mapping scenarios.

Original languageEnglish (US)
Article number1464794
Pages (from-to)1138-1141
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: May 23 2005May 26 2005


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