Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations. We present two methodologies for mapping an FFT computation onto a CDMA-based star topology network-on-chip (NoC) architecture. These implementations reduce the FFT data shuffling time and simplify the data flow between processing elements. The design has been modeled using SystemC and the simulation results provide throughput and latency performance metrics for the different mapping scenarios.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 2005|
|Event||IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan|
Duration: May 23 2005 → May 26 2005