Parallel decoding of interleaved single parity check turbo product codes

Yanni Chen, Keshab K Parhi

Research output: Chapter in Book/Report/Conference proceedingChapter

3 Scopus citations

Abstract

In this paper, both complexity and performance aspects of serially concatenated 2-D single parity check turbo product codes are investigated. The extremely simple Max-Log-MAP decoding is alternatively derived with only three additions needed to compute each bit's extrinsic information. Parallel decoding structure is proposed to increase the decoding throughput while a new helical interleaver is constructed to further improve the coding gain. For performance evaluation, (16, 14, 2)2 single parity check turbo product codes with code rate 0.766 over an AWGN channel using QPSK are considered. The simulation results using Max-Log-MAP decoding show that it can achieve BER of 10-5 at SNR of 3.8 dB with 8 iterations. Compared to the same rate and codeword length turbo product code composed of extended Hamming codes, the considered scheme can achieve similar performance with much less complexity. Other implementation issues such as the finite precision analysis and efficient sorting circuit design are also presented.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on Signal Processing Systems, SiPS
Subtitle of host publicationDesign and Implementation
Pages27-32
Number of pages6
ISBN (Electronic)0780375874
DOIs
StatePublished - Jan 1 2002

Keywords

  • AWGN channels
  • Bit error rate
  • Circuit synthesis
  • Concatenated codes
  • Iterative decoding
  • Parity check codes
  • Product codes
  • Quadrature phase shift keying
  • Sorting
  • Throughput

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  • Cite this

    Chen, Y., & Parhi, K. K. (2002). Parallel decoding of interleaved single parity check turbo product codes. In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation (pp. 27-32). [1049680] https://doi.org/10.1109/SIPS.2002.1049680