Parallel architecture with resistive crosspoint array for dictionary learning acceleration

Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai Yu Chen, Binbin Lin, Jieping Ye, Sarma Vrudhula, Shimeng Yu, Yu Cao, Jae Sun Seo

Research output: Contribution to journalArticlepeer-review

52 Scopus citations


This paper proposes a parallel architecture with resistive crosspoint array. The design of its two essential operations, read and write, is inspired by the biophysical behavior of a neural system, such as integrate-and-fire and local synapse weight update. The proposed hardware consists of an array with resistive random access memory (RRAM) and CMOS peripheral circuits, which perform matrix-vector multiplication and dictionary update in a fully parallel fashion, at the speed that is independent of the matrix dimension. The read and write circuits are implemented in 65 nm CMOS technology and verified together with an array of RRAM device model built from experimental data. The overall system exploits array-level parallelism and is demonstrated for accelerated dictionary learning tasks. As compared to software implementation running on a 8-core CPU, the proposed hardware achieves more than 3000× speedup, enabling high-speed feature extraction on a single chip.

Original languageEnglish (US)
Article number07116611
Pages (from-to)194-204
Number of pages11
JournalIEEE Journal on Emerging and Selected Topics in Circuits and Systems
Issue number2
StatePublished - Jun 1 2015
Externally publishedYes

Bibliographical note

Publisher Copyright:
© 2011 IEEE.


  • CMOS integration
  • dictionary learning
  • memristive device
  • parallel computing
  • resistive crosspoint array


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