Parallel architecture for large scale production systems

K. W. Hwang; J. Tan; J. H. Wang; J. Srivastava; W. T. Tsai

Parallel architecture for large scale production systems

K. W. Hwang, J. Tan, J. H. Wang, J. Srivastava, W. T. Tsai

Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

The authors present an architecture, suitable for implementation on a shared memory multiprocessor system, in which all the phases can run in parallel. Running multiple match, execution, and select phases causes subtle synchronization problems, which if not resolved can lead to altered semantics. The proposed architecture uses a lock and interference manager and a scheduler to resolve the possible synchronization conflicts. A new lock which provides concurrency beyond the standard two-phase locking in databases is used. The conflict resolution phase has been formalized as a scheduling problem. The approach taken is conservative in the sense that the scheduler performs careful analysis (interference avoidance and abort avoidance tests) to prevent interference, abort, and blocking.

Original language	English (US)
Title of host publication	IEEE Int Workshop Tools Artif Intell Archit Lang Algorithms
Editors	Anon
Publisher	Publ by IEEE
Pages	27-33
Number of pages	7
ISBN (Print)	0818619848
State	Published - 1989
Event	IEEE International Workshop on Tools for Artificial Intelligence: Architectures, Languages and Algorithms - Fairfax, VA, USA Duration: Oct 23 1989 → Oct 25 1989

Publication series

Name	IEEE Int Workshop Tools Artif Intell Archit Lang Algorithms

Other

Other	IEEE International Workshop on Tools for Artificial Intelligence: Architectures, Languages and Algorithms
City	Fairfax, VA, USA
Period	10/23/89 → 10/25/89

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Hwang, KW, Tan, J, Wang, JH, Srivastava, J & Tsai, WT 1989, Parallel architecture for large scale production systems. in Anon (ed.), IEEE Int Workshop Tools Artif Intell Archit Lang Algorithms. IEEE Int Workshop Tools Artif Intell Archit Lang Algorithms, Publ by IEEE, pp. 27-33, IEEE International Workshop on Tools for Artificial Intelligence: Architectures, Languages and Algorithms, Fairfax, VA, USA, 10/23/89.

@inproceedings{c84b91fb545641f4aaf3c511dc1c0dac,

title = "Parallel architecture for large scale production systems",

abstract = "The authors present an architecture, suitable for implementation on a shared memory multiprocessor system, in which all the phases can run in parallel. Running multiple match, execution, and select phases causes subtle synchronization problems, which if not resolved can lead to altered semantics. The proposed architecture uses a lock and interference manager and a scheduler to resolve the possible synchronization conflicts. A new lock which provides concurrency beyond the standard two-phase locking in databases is used. The conflict resolution phase has been formalized as a scheduling problem. The approach taken is conservative in the sense that the scheduler performs careful analysis (interference avoidance and abort avoidance tests) to prevent interference, abort, and blocking.",

author = "Hwang, {K. W.} and J. Tan and Wang, {J. H.} and J. Srivastava and Tsai, {W. T.}",

year = "1989",

language = "English (US)",

isbn = "0818619848",

series = "IEEE Int Workshop Tools Artif Intell Archit Lang Algorithms",

publisher = "Publ by IEEE",

pages = "27--33",

editor = "Anon",

booktitle = "IEEE Int Workshop Tools Artif Intell Archit Lang Algorithms",

note = "IEEE International Workshop on Tools for Artificial Intelligence: Architectures, Languages and Algorithms ; Conference date: 23-10-1989 Through 25-10-1989",

}

TY - GEN

T1 - Parallel architecture for large scale production systems

AU - Hwang, K. W.

AU - Tan, J.

AU - Wang, J. H.

AU - Srivastava, J.

AU - Tsai, W. T.

PY - 1989

Y1 - 1989

N2 - The authors present an architecture, suitable for implementation on a shared memory multiprocessor system, in which all the phases can run in parallel. Running multiple match, execution, and select phases causes subtle synchronization problems, which if not resolved can lead to altered semantics. The proposed architecture uses a lock and interference manager and a scheduler to resolve the possible synchronization conflicts. A new lock which provides concurrency beyond the standard two-phase locking in databases is used. The conflict resolution phase has been formalized as a scheduling problem. The approach taken is conservative in the sense that the scheduler performs careful analysis (interference avoidance and abort avoidance tests) to prevent interference, abort, and blocking.

AB - The authors present an architecture, suitable for implementation on a shared memory multiprocessor system, in which all the phases can run in parallel. Running multiple match, execution, and select phases causes subtle synchronization problems, which if not resolved can lead to altered semantics. The proposed architecture uses a lock and interference manager and a scheduler to resolve the possible synchronization conflicts. A new lock which provides concurrency beyond the standard two-phase locking in databases is used. The conflict resolution phase has been formalized as a scheduling problem. The approach taken is conservative in the sense that the scheduler performs careful analysis (interference avoidance and abort avoidance tests) to prevent interference, abort, and blocking.

UR - http://www.scopus.com/inward/record.url?scp=0024878699&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024878699&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0024878699

SN - 0818619848

T3 - IEEE Int Workshop Tools Artif Intell Archit Lang Algorithms

SP - 27

EP - 33

BT - IEEE Int Workshop Tools Artif Intell Archit Lang Algorithms

A2 - Anon, null

PB - Publ by IEEE

T2 - IEEE International Workshop on Tools for Artificial Intelligence: Architectures, Languages and Algorithms

Y2 - 23 October 1989 through 25 October 1989

ER -

Parallel architecture for large scale production systems

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