Overlapped message passing for quasi-cyclic low-density parity check codes

Yanni Chen, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

130 Scopus citations

Abstract

In this paper, a systematic approach is proposed to develop a high throughput decoder for quasi-cyclic low-density parity check (LDPC) codes, whose parity check matrix is constructed by circularly shifted identity matrices. Based on the properties of quasi-cyclic LDPC codes, the two stages of belief propagation decoding algorithm, namely, check node update and variable node update, could be overlapped and thus the overall decoding latency is reduced. To avoid the memory access conflict, the maximum concurrency of the two stages is explored by a novel scheduling algorithm. Consequently, the decoding throughput could be increased by about twice assuming dual-port memory is available.

Original languageEnglish (US)
Pages (from-to)1106-1113
Number of pages8
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume51
Issue number6
DOIs
StatePublished - Jun 2004

Bibliographical note

Funding Information:
This work was supported by the National Natural Science Foundation of China [grant numbers 11472066 and 11672050]; the Chongqing University Graduate Student Research Innovation Project [grant number CYS16009]; the Program for New Century Excellent Talents in University [grant number nect-13-0634]; the Fundamental Research Funds for the Central Universities [grant number CDJZR14328801]; and China Postdoctoral Science Foundation [grant number 2016M592636].

Keywords

  • High throughput
  • Low-density parity check (LDPC) codes
  • Overlapped message passing (MP)
  • Quasi-cyclic codes

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