## Abstract

In low-density parity-check (LDPC) code decoding with the iterative sum-product algorithm (SPA), due to the randomness of a parity-check matrix H, the overlapping of check node processing unit (CNU) and variable node processing unit (VNU) in the same clock cycle is difficult. This paper demonstrates that overlapped decoding can be exploited as long as the LDPC matrix is composed of identity matrices and their cyclic-shifted matrices, i.e., a parity-check matrix H belongs to a class of quasi-cyclic LDPC codes. It is shown that the number of clock cycles required for decoding can be reduced by 50% when overlapped decoding is applied to a (3,6)-regular LDPC code decoder.

Original language | English (US) |
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Pages (from-to) | 113-117 |

Number of pages | 5 |

Journal | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation |

State | Published - Dec 1 2004 |

Event | 2004 IEEE Workshop on Signal Processing Systems Design and Implementation, Proceedings - Austin, TX, United States Duration: Oct 13 2004 → Oct 15 2004 |