Nanometer-scale circuits are fundamentally different from those built in their predecessor technologies in that they are subject to a wide range of new effects that induce on-chip variations. These include effects associated with printing finer geometry features, increased atomic-scale effects, and increased on-chip power densities, and are manifested as variations in process and environmental parameters and as circuit aging effects. The impact of such variations on key circuit performance metrics is quite significant, resulting in parametric variations in the timing and power, and potentially catastrophic failure due to reliability and aging effects. Such problems have led to a revolution in the way that chips are designed in the presence of such uncertainties, both in terms of performance analysis and optimization. This paper presents an overview of the root causes of these variations and approaches for overcoming their effects.
|Original language||English (US)|
|Number of pages||14|
|Journal||IEEE Journal on Emerging and Selected Topics in Circuits and Systems|
|State||Published - Mar 2011|
Bibliographical noteFunding Information:
Manuscript received January 04, 2011; revised February 15, 2011; accepted February 26, 2011. Date of publication May 02, 2011; date of current version May 25, 2011. This work was supported in part by the SRC under Contract 2007-TJ-1572 and by the National Science Foundation under Awards CCF-0634802 and CCF-1017778.
- On-chip sensors
- power supply variations
- process variations
- thermal variations
- thermally aware design