Optimum primitive polynomials for low-area low-power finite field semi-systolic multipliers

Leilei Song, Keshab K Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Finite field multipliers are the basic building blocks in many applications such as cryptography, error-control coding and digital signal processing. The design of efficient dedicated finite field multiplier architectures can lead to dramatic improvement on the overall system performance. For a given multiplier architecture, its hardware complexity, computation time and power consumption are highly dependent on primitive polynomial p(x). Generally, primitive polynomial is selected to optimize application-oriented parameters, such as minimizing decoding error probability in error-control coding. A secondary selection criterion should be to improve the implementation efficiency, i.e., minimizing area and power consumption while meeting the speed requirement. In this paper, the effects of different primitive polynomials on area and power consumption of semi-systolic finite field multipliers are analyzed. It is shown that the hardware complexity and the total number of transitions can be reduced by selecting the primitive polynomials with less Hamming weight. The optimum primitive polynomials for low area and low power semi-systolic multipliers over different finite field GF(2m) are provided based on the analysis results.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on Signal Processing Systems, SiPS
Subtitle of host publicationDesign and Implementation
PublisherIEEE
Pages375-384
Number of pages10
StatePublished - Dec 1 1997
EventProceedings of the 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation - Leicester, UK
Duration: Nov 3 1997Nov 5 1997

Other

OtherProceedings of the 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation
CityLeicester, UK
Period11/3/9711/5/97

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