## Abstract

Finite field multipliers are the basic building blocks in many applications such as cryptography, error-control coding and digital signal processing. The design of efficient dedicated finite field multiplier architectures can lead to dramatic improvement on the overall system performance. For a given multiplier architecture, its hardware complexity, computation time and power consumption are highly dependent on primitive polynomial p(x). Generally, primitive polynomial is selected to optimize application-oriented parameters, such as minimizing decoding error probability in error-control coding. A secondary selection criterion should be to improve the implementation efficiency, i.e., minimizing area and power consumption while meeting the speed requirement. In this paper, the effects of different primitive polynomials on area and power consumption of semi-systolic finite field multipliers are analyzed. It is shown that the hardware complexity and the total number of transitions can be reduced by selecting the primitive polynomials with less Hamming weight. The optimum primitive polynomials for low area and low power semi-systolic multipliers over different finite field GF(2^{m}) are provided based on the analysis results.

Original language | English (US) |
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Title of host publication | IEEE Workshop on Signal Processing Systems, SiPS |

Subtitle of host publication | Design and Implementation |

Publisher | IEEE |

Pages | 375-384 |

Number of pages | 10 |

State | Published - Dec 1 1997 |

Event | Proceedings of the 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation - Leicester, UK Duration: Nov 3 1997 → Nov 5 1997 |

### Other

Other | Proceedings of the 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation |
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City | Leicester, UK |

Period | 11/3/97 → 11/5/97 |