Optimizing loop operation and dataflow in FPGA acceleration of deep convolutional neural networks

Keyphrases

• Deep Convolutional Neural Network (deep CNN) 100%
• FPGA Acceleration 100%
• Convolutional Neural Network Accelerator 100%
• Loop Operation 100%
• Memory Access 50%
• Acceleration Schemes 50%
• Loop Optimization 50%
• Data Movement 50%
• Accelerator Architectures 50%
• High Performance 25%
• Three-dimensional (3D) 25%
• Latency 25%
• Design Phase 25%
• Hardware Design 25%
• Four-level 25%
• Hardware Cost 25%
• Resource Utilization 25%
• FPGA Implementation 25%
• Optimization Techniques 25%
• Loop Unrolling 25%
• Design Objectives 25%
• Multiple Design 25%
• Data Reuse 25%
• Loop Tiling 25%
• Altera 25%
• Convolutional Layer 25%
• Convolutional Neural Network Model 25%
• VGG16 25%
• Variable Configuration 25%
• Arria 10 25%
• Convolutional Accelerator 25%
• VGG Model 25%
• Memory Data 25%
• Multiply-accumulate 25%
• Large Design Space 25%
• Convolutional Neural Network Algorithm 25%
• Loop Interchange 25%

Computer Science

• Loop Operation 100%
• Convolutional Neural Network 100%
• Deep Convolutional Neural Networks 100%
• Field Programmable Gate Arrays 100%
• Memory Access 28%
• Computer Hardware 28%
• Optimization Technique 14%
• Hardware Design 14%
• Hardware Cost 14%
• Neural Network Model 14%
• Loop Unrolling 14%
• Design Phase 14%
• Data Reuse 14%
• Multiple Design 14%
• Loop Tiling 14%
• Convolution Layer 14%
• Loop Interchange 14%
• Configuration Variable 14%
• VGG-16 14%
• Resource Utilisation 14%
• Design Objective 14%
• Artificial Neural Network 14%