Optimized self-tuning for circuit aging

Engineering

• Sleep Mode 100%
• Policy Control 100%
• Design Guideline 50%
• Simulation Result 50%
• Metrics 50%
• Design Constraint 50%
• Aging Time 50%
• Control Action 50%
• Clock Frequency 50%
• Active Mode 50%
• Computational Power 50%
• Performance Constraint 50%
• Control Dynamics 50%
• Supply Voltage 50%
• Clock Cycle 50%

Computer Science

• Supply Voltage 100%
• Clock Cycle 100%
• Benchmark Circuit 100%
• Power Efficiency 100%
• Clock Frequency 100%
• Computational Power 100%
• Control Action 100%
• Design Constraint 100%

Keyphrases

• Aging 100%
• Circuit Aging 100%
• Control Policy 33%
• Sleep Mode 33%
• Self-tuning Parameters 33%
• System Design 16%
• Design Guidelines 16%
• Aging Model 16%
• Power Efficiency 16%
• Design Requirements 16%
• Dynamic Control 16%
• Efficiency Metrics 16%
• Clock Frequency 16%
• Stress Measurement 16%
• Optimization Control 16%
• Analysis Design 16%
• Benchmark Circuits 16%
• Control Actions 16%
• Active Mode 16%
• 45 Nm CMOS Technology 16%
• Computational Power 16%
• Performance Constraints 16%
• Recovery Effect 16%
• Total Energy Consumed 16%
• Active Sleep 16%
• Dynamic Cooling 16%
• Supply Voltage Frequency 16%
• On-state 16%
• Real-time Aging 16%