Optimized circuit failure prediction for aging: Practicality and promise

Mridul Agarwal, Varsha Balakrishnan, Anshuman Bhuyan, Kyunglok Kim, Bipul C. Paul, Wenping Wang, Bo Yang, Yu Cao, Subhasish Mitra

Research output: Chapter in Book/Report/Conference proceedingConference contribution

123 Scopus citations


Circuit failure prediction is used to predict occurrences of circuit failures, during system operation, before errors appear in system data and states. This technique is applicable for overcoming major scaled-CMOS reliability challenges posed by aging mechanisms such as Negative-Bias- Temperature-Instability (NBTI). This is possible because of the gradual nature of degradation associated with such aging mechanisms. Circuit failure prediction uses special on-chip circuits called aging sensors. In this paper, we experimentally demonstrate correct functionality and practicality of two flavors of flip-flop designs with built-in aging sensors using 90nm test chips. We also present an aging-aware timing analysis technique to strategically place such flip-flops with built-in aging sensors at selective locations inside a chip for effective circuit failure prediction. This aging-aware timing analysis approach also minimizes the chip-level area impact of such aging sensors. Results from two 90nm designs demonstrate the practicality and effectiveness of optimized circuit failure prediction with overall chip-level area impact of 2.5% and 0.6%.

Original languageEnglish (US)
Title of host publicationProceedings - International Test Conference 2008, ITC 2008
StatePublished - 2008
Externally publishedYes
EventInternational Test Conference 2008, ITC 2008 - Santa Clara, CA, United States
Duration: Oct 28 2008Oct 30 2008

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539


ConferenceInternational Test Conference 2008, ITC 2008
Country/TerritoryUnited States
CitySanta Clara, CA


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