Optimization of staggered heterojunction p-TFETs for LSTP and LOP applications

E. Baravelli, E. Gnani, R. Grassi, A. Gundi, G. Baccarani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Effect of transverse quantization on the broken vs. staggered band lineup of InAs/Al xGa1-xSb TFETs is investigated, showing that cross-sections up to 1 0nm lead to staggered configurations for any value of the Al mole fraction x. Device performance is optimized as a function of cross-sectional size, Al content and possible source/channel underlap, while ensuring low standby power (LSTP) or low operating power (LOP) compatible off-current levels. Guidelines are provided and an 'optimal' design is proposed which provides a minimum sub-threshold slope (SS) of 7.2 mV/dec along with a maximum on-state current (IOn) of 175μ/μm.

Original languageEnglish (US)
Title of host publication71st Device Research Conference, DRC 2013 - Conference Digest
Pages67-68
Number of pages2
DOIs
StatePublished - Dec 16 2013
Event71st Device Research Conference, DRC 2013 - Notre Dame, IN, United States
Duration: Jun 23 2013Jun 26 2013

Other

Other71st Device Research Conference, DRC 2013
CountryUnited States
CityNotre Dame, IN
Period6/23/136/26/13

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  • Cite this

    Baravelli, E., Gnani, E., Grassi, R., Gundi, A., & Baccarani, G. (2013). Optimization of staggered heterojunction p-TFETs for LSTP and LOP applications. In 71st Device Research Conference, DRC 2013 - Conference Digest (pp. 67-68). [6633796] https://doi.org/10.1109/DRC.2013.6633796