Optimization of staggered heterojunction p-TFETs for LSTP and LOP applications

E. Baravelli; E. Gnani; R. Grassi; A. Gundi; G. Baccarani

doi:10.1109/DRC.2013.6633796

Optimization of staggered heterojunction p-TFETs for LSTP and LOP applications

E. Baravelli, E. Gnani, R. Grassi, A. Gundi, G. Baccarani

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

Effect of transverse quantization on the broken vs. staggered band lineup of InAs/Al _xGa_1-xSb TFETs is investigated, showing that cross-sections up to 1 0nm lead to staggered configurations for any value of the Al mole fraction x. Device performance is optimized as a function of cross-sectional size, Al content and possible source/channel underlap, while ensuring low standby power (LSTP) or low operating power (LOP) compatible off-current levels. Guidelines are provided and an 'optimal' design is proposed which provides a minimum sub-threshold slope (SS) of 7.2 mV/dec along with a maximum on-state current (I_On) of 175μ/μm.

Original language	English (US)
Title of host publication	71st Device Research Conference, DRC 2013 - Conference Digest
Pages	67-68
Number of pages	2
DOIs	https://doi.org/10.1109/DRC.2013.6633796
State	Published - Dec 16 2013
Event	71st Device Research Conference, DRC 2013 - Notre Dame, IN, United States Duration: Jun 23 2013 → Jun 26 2013

Other

Other	71st Device Research Conference, DRC 2013
Country/Territory	United States
City	Notre Dame, IN
Period	6/23/13 → 6/26/13

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10.1109/DRC.2013.6633796

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title = "Optimization of staggered heterojunction p-TFETs for LSTP and LOP applications",

abstract = "Effect of transverse quantization on the broken vs. staggered band lineup of InAs/Al xGa1-xSb TFETs is investigated, showing that cross-sections up to 1 0nm lead to staggered configurations for any value of the Al mole fraction x. Device performance is optimized as a function of cross-sectional size, Al content and possible source/channel underlap, while ensuring low standby power (LSTP) or low operating power (LOP) compatible off-current levels. Guidelines are provided and an 'optimal' design is proposed which provides a minimum sub-threshold slope (SS) of 7.2 mV/dec along with a maximum on-state current (IOn) of 175μ/μm.",

author = "E. Baravelli and E. Gnani and R. Grassi and A. Gundi and G. Baccarani",

year = "2013",

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doi = "10.1109/DRC.2013.6633796",

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T1 - Optimization of staggered heterojunction p-TFETs for LSTP and LOP applications

AU - Baravelli, E.

AU - Gnani, E.

AU - Grassi, R.

AU - Gundi, A.

AU - Baccarani, G.

PY - 2013/12/16

Y1 - 2013/12/16

N2 - Effect of transverse quantization on the broken vs. staggered band lineup of InAs/Al xGa1-xSb TFETs is investigated, showing that cross-sections up to 1 0nm lead to staggered configurations for any value of the Al mole fraction x. Device performance is optimized as a function of cross-sectional size, Al content and possible source/channel underlap, while ensuring low standby power (LSTP) or low operating power (LOP) compatible off-current levels. Guidelines are provided and an 'optimal' design is proposed which provides a minimum sub-threshold slope (SS) of 7.2 mV/dec along with a maximum on-state current (IOn) of 175μ/μm.

AB - Effect of transverse quantization on the broken vs. staggered band lineup of InAs/Al xGa1-xSb TFETs is investigated, showing that cross-sections up to 1 0nm lead to staggered configurations for any value of the Al mole fraction x. Device performance is optimized as a function of cross-sectional size, Al content and possible source/channel underlap, while ensuring low standby power (LSTP) or low operating power (LOP) compatible off-current levels. Guidelines are provided and an 'optimal' design is proposed which provides a minimum sub-threshold slope (SS) of 7.2 mV/dec along with a maximum on-state current (IOn) of 175μ/μm.

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M3 - Conference contribution

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BT - 71st Device Research Conference, DRC 2013 - Conference Digest

T2 - 71st Device Research Conference, DRC 2013

Y2 - 23 June 2013 through 26 June 2013

ER -

Optimization of staggered heterojunction p-TFETs for LSTP and LOP applications

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