Skip to main navigation
Skip to search
Skip to main content
Experts@Minnesota Home
Home
Profiles
Research units
University Assets
Projects and Grants
Research output
Datasets
Press/Media
Activities
Fellowships, Honors, and Prizes
Impacts
Search by expertise, name or affiliation
Optimal power/Performance pipelining for error resilient processors
Nicolas Zea
,
John Sartori
, Ben Ahrens
, Rakesh Kumar
Electrical and Computer Engineering
Research output
:
Chapter in Book/Report/Conference proceeding
›
Conference contribution
5
Scopus citations
Overview
Fingerprint
Fingerprint
Dive into the research topics of 'Optimal power/Performance pipelining for error resilient processors'. Together they form a unique fingerprint.
Sort by
Weight
Alphabetically
Keyphrases
Power Performance
100%
Error Resilience
100%
Optimal Power
100%
Timing Speculation
21%
Significant Energy
14%
Resilience Mechanisms
14%
Circuit Structure
14%
Energy Saving
7%
Energy Efficiency
7%
Error Rate
7%
Rate of Increase
7%
Design Methodology
7%
Microarchitecture
7%
Analytical Results
7%
Energy Efficiency Benefits
7%
Operating Point
7%
Analytical Model
7%
Input Voltage
7%
Agnostic
7%
Recovery Mechanism
7%
Processor Design
7%
Cycle-accurate Simulation
7%
Error Recovery
7%
Processor Pipeline
7%
Pipeline Structure
7%
Resiliency Mechanisms
7%
Long pipeline
7%
Irregular Workloads
7%
Energy Efficiency Metrics
7%
Simulation-based Model
7%
Computer Science
Pipelining
100%
Error Resilience
100%
optimal power
100%
Energy Efficiency
50%
Microarchitecture
16%
Processor Design
16%
Pipeline Processor
16%
Analytical Model
16%
Operating Point
16%