The problem of designing individual macrocells for a library for low power and high speed is addressed here, and a new technique for optimization using posynomial approximating functions is devised. In the design of each macrocell, optimality in design is critical and highly accurate techniques for measuring the performance are required during optimization. This paper presents methods for accurately estimating the worst-case contribution of the power and delay of a ceil to a circuit. The program uses circuit-level simulation to calculate the power dissipation and delay of the cell with the highest accuracy. A rationale for using arbitrary degree posynomial modeling functions for area, delay, and power modeling is presented. The problem is then formulated as a convex programming problem, and a rigorous optimization technique is used to arrive at the optimal macrocell.
|Original language||English (US)|
|Number of pages||7|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|State||Published - 1996|
Bibliographical noteFunding Information:
Manuscript received August 12, 1994; revised August 25, 1995 and March 1 I, 1996. This work was supported in part by the National Science Foundation under Contract MIP-9502556. This paper was recommended by Associate Editor T. Yoshimura. P. K. Sancheti was with the Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 5001 1 USA. He is now with Cadence Design Systems, Chelmsford, MA 01824 USA. S. S. Sapatnekar is with the Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 5001 1 USA. Publisher Item Identifier S 0278-0070(96)06727-9.