Optimal decoupling capacitor sizing and placement for standard-cell layout designs

Keyphrases

• Standard Cell Placement 100%
• Cell Layout Design 100%
• Decoupling Capacitance 100%
• Decoupling Capacitor 100%
• Capacitor Sizing 100%
• Capacitor Placement 100%
• Power Grid 66%
• High Performance 33%
• Integrated Circuits 33%
• Low Voltage 33%
• First-order 33%
• Degrees of Freedom 33%
• Operating Frequency 33%
• Quadratic Programming 33%
• On-chip Power Grid 33%
• Convolution Method 33%
• Nonlinear Optimization 33%
• Piecewise Linear 33%
• Order Sensitivity 33%
• Chip Area 33%
• Application Specific Integrated Circuits 33%
• Noise Abatement 33%
• Fast Convolution 33%
• Automated Sizing 33%
• Programming Solver 33%
• Sensitivity Method 33%
• Automated Placement 33%
• Voltage Power 33%
• Linear Compression 33%
• International Technology Roadmap for Semiconductors 33%
• Technology Scaling 33%
• High Energy Dissipation 33%
• Adjoint Sensitivity Method 33%

Engineering

• Power Grid 100%
• Decoupling Capacitor 100%
• Power Supply 33%
• Experimental Result 33%
• Degree of Freedom 33%
• Energy Dissipation 33%
• Operating Frequency 33%
• Integrated Circuit 33%
• Nonlinear Optimization 33%
• Chip Area 33%
• Supply Voltage 33%
• Application Specific Integrated Circuit 33%

Computer Science

• Decoupling Capacitance 100%
• Decoupling Capacitor 100%
• Quadratic Programming 33%
• Power Dissipation 33%
• Power Supply Voltage 33%
• piecewise linear 33%
• Integrated Circuits 33%
• Experimental Result 33%
• Operating Frequency 33%
• Application Specific Integrated Circuit 33%