TY - GEN
T1 - Online digital data processing for the T2K fine grained detector
AU - Amaudruz, P. A.
AU - Bishop, D.
AU - Braam, N.
AU - Gutjahr, C.
AU - Karlen, D.
AU - Hasanen, R.
AU - Henderson, R.
AU - Honkanen, N.
AU - Kirby, B.
AU - Lindner, T.
AU - Miller, A.
AU - Mizouchi, K.
AU - Ohlmann, C.
AU - Olchanski, K.
AU - Oser, S.
AU - Pearson, C.
AU - Poffenberger, P.
AU - Poutissou, R.
AU - Retire, F.
AU - Tanaka, H.
AU - Zalipska, J.
AU - Wilking, M.
PY - 2010
Y1 - 2010
N2 - The T2K Fine Grained Detector is an active neutrino target that uses segmented scintillator bars to observe short-range particle tracks. 8448 multi-pixel photon counters coupled to wavelength shifting fibres detect scintillator light. An application specific integrated circuit shapes the MPPC waveform and uses a switched capacitor array to store up to 511 analog samples over 10.24μs. High and low attenuation channels for each MPPC improve dynamic range. 12-bit serial quad-ADCs digitize ASIC analog output and interface with a field programmable gate array, while each FPGA simultaneously reads out four ADCs and saves the synchronized samples in an external digital memory. The system produces 13.5 MB of uncompressed data per acquisition with a target trigger rate of 20 Hz, and requires zero suppression to reduce data size and readout time. Firmware based data compression uses an online pulse-finder that decides whether to output pulse height information, a section of waveform, or to suppress all data. The front end FPGA transfers formatted data to collector cards through a 2 Gb/s optical fiber interface using an efficient custom protocol. We have evaluated the performance of the FGD electronics system and the quality of its online data compression through the course of a physics data run.
AB - The T2K Fine Grained Detector is an active neutrino target that uses segmented scintillator bars to observe short-range particle tracks. 8448 multi-pixel photon counters coupled to wavelength shifting fibres detect scintillator light. An application specific integrated circuit shapes the MPPC waveform and uses a switched capacitor array to store up to 511 analog samples over 10.24μs. High and low attenuation channels for each MPPC improve dynamic range. 12-bit serial quad-ADCs digitize ASIC analog output and interface with a field programmable gate array, while each FPGA simultaneously reads out four ADCs and saves the synchronized samples in an external digital memory. The system produces 13.5 MB of uncompressed data per acquisition with a target trigger rate of 20 Hz, and requires zero suppression to reduce data size and readout time. Firmware based data compression uses an online pulse-finder that decides whether to output pulse height information, a section of waveform, or to suppress all data. The front end FPGA transfers formatted data to collector cards through a 2 Gb/s optical fiber interface using an efficient custom protocol. We have evaluated the performance of the FGD electronics system and the quality of its online data compression through the course of a physics data run.
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U2 - 10.1109/RTC.2010.5750338
DO - 10.1109/RTC.2010.5750338
M3 - Conference contribution
AN - SCOPUS:79956057400
SN - 9781424471096
T3 - Conference Record - 2010 17th IEEE-NPSS Real Time Conference, RT10
BT - Conference Record - 2010 17th IEEE-NPSS Real Time Conference, RT10
T2 - 2010 17th IEEE-NPSS Real Time Conference, RT10
Y2 - 24 May 2010 through 28 May 2010
ER -