Abstract
Wafer packing is a process of combining multiple chip designs on the same water such that the fabrication cost can be shared by several designs and hence reduced. This technique is widely used for designs that require a small number of dies or chips. It is essential to have computer algorithms to decide how to allocate designs to wafers in order to reduce the total fabrication cost. Based on different wafer fabrication techniques, two versions of the wafer packing problem are formulated. We study different variations for each version. We present algorithms to find optimal solutions for these variations which are polynomial-time solvable. We also present heuristic algorithms for those proven to be NP-hard. The effectiveness of the proposed algorithms is demonstrated by experimental results.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1382-1388 |
| Number of pages | 7 |
| Journal | IEEE Transactions on Computers |
| Volume | 42 |
| Issue number | 11 |
| DOIs | |
| State | Published - Nov 1993 |
Bibliographical note
Funding Information:Manuscript received February 26, 1990; revised October 31, 1991 and March 1, 1993. This work was supported in part by NSF Grant MIP-9007168. D. H. C. Du is with the Department of Computer Science, University of Minnesota, Minneapolis, MN 55455. I. Lin was with the Department of Computer Science, University of Minnesota, Minneapolis, MN 55455. He is now with Silicon Graphics Inc., Mountain View, CA 94043. K. C. Chang was with the Department of Computer Science, University of Minnesota, Minneapolis, MN 55455. He is now with Boeing Electronics, Seattle, WA 98124. IEEE Log Number 9212703.