On The Performance/Complexity Tradeoff in Block Turbo Decoder Design

Zhipei Chi, Leilei Song, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

17 Scopus citations


In this letter, tradeoffs between very large scale integration implementation complexity and performance of block turbo decoders are explored. We address low-complexity design strategies on choosing the scaling factor of the log extrinsic information and on reducing the number of hard-decision decodings during a Chase search.

Original languageEnglish (US)
Pages (from-to)173-175
Number of pages3
JournalIEEE Transactions on Communications
Issue number2
StatePublished - Feb 2004

Bibliographical note

Funding Information:
Paper approved by W. E. Ryan, the Editor for Modulation, Coding, and Equalization of the IEEE Communications Society. Manuscript received February 7, 2002; revised January 6, 2003 and June 24, 2003. This work was supported in part by Summer Intern Program 2000, Bell Labs, Lucent Technologies, and in part by the Army Research Office under Contract DA/DAAD19-01-1-0705. This paper was presented in part at the IEEE International Symposium on Circuits and Systems, Sydney, Australia, May 2001.


  • Block codes
  • Forward error correction (FEC)
  • Iterative decoding
  • Low-complexity design
  • Turbo codes


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