On the high-speed VLSI implementation of errors-and-erasures correcting Reed-Solomon decoders

Tong Zhang; Keshab K. Parhi

doi:10.1145/505306.505326

On the high-speed VLSI implementation of errors-and-erasures correcting Reed-Solomon decoders

Tong Zhang
, Keshab K. Parhi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

16 Scopus citations

Abstract

Recently a novel algorithm transformation was proposed to reduce the critical path of Berlekamp-Massey algorithm implementation for errors-alone Reed-Solomon decoding. In this paper, we apply the same methodology to transform the Berlekamp-Massey algorithm for errors-and-erasures RS decoding. We present a regular hardware architecture to implement the reformulated Berlekamp-Massey algorithm, which can achieve high throughput. Moreover, an operation scheduling scheme is proposed to further reduce the hardware complexity without loss of throughput.

Original language	English (US)
Title of host publication	GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI
Publisher	Association for Computing Machinery, Inc
Pages	89-93
Number of pages	5
ISBN (Electronic)	1581134622, 9781581134629
DOIs	https://doi.org/10.1145/505306.505326
State	Published - Apr 18 2002
Event	12th ACM Great Lakes Symposium on VLSI, GLSVLSI 2002 - New York, United States Duration: Apr 18 2002 → Apr 19 2002

Publication series

Name	GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI

Other

Other	12th ACM Great Lakes Symposium on VLSI, GLSVLSI 2002
Country/Territory	United States
City	New York
Period	4/18/02 → 4/19/02

Bibliographical note

Publisher Copyright:
Copyright 2002 ACM.

Keywords

Berlekamp-massey algorithm
Erasure
Reed-solomon codes
VLSI architectures

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10.1145/505306.505326

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Zhang, T., & Parhi, K. K. (2002). On the high-speed VLSI implementation of errors-and-erasures correcting Reed-Solomon decoders. In GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI (pp. 89-93). (GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI). Association for Computing Machinery, Inc. https://doi.org/10.1145/505306.505326

On the high-speed VLSI implementation of errors-and-erasures correcting Reed-Solomon decoders. / Zhang, Tong; Parhi, Keshab K.
GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI. Association for Computing Machinery, Inc, 2002. p. 89-93 (GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhang, T & Parhi, KK 2002, On the high-speed VLSI implementation of errors-and-erasures correcting Reed-Solomon decoders. in GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI. GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI, Association for Computing Machinery, Inc, pp. 89-93, 12th ACM Great Lakes Symposium on VLSI, GLSVLSI 2002, New York, United States, 4/18/02. https://doi.org/10.1145/505306.505326

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On the high-speed VLSI implementation of errors-and-erasures correcting Reed-Solomon decoders

Abstract

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Keywords

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