On Improving the Write Responsiveness for Host-Aware SMR Drives

Ming Chang Yang, Yuan Hao Chang, Fenggang Wu, Tei Wei Kuo, David H Du

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper presents a Virtual Persistent Cache design to remedy the long latency behavior and to ultimately improve the write responsiveness of the Host-Aware Shingled Magnetic Recording (HA-SMR) drives. Our design keeps the cost-effective model of the existing HA-SMR drives, but at the same time asks the great help from the host system for adaptively providing some computing and management resources to improve the drive performance when needed. The technical contribution is to trick the HA-SMR drives by smartly reshaping the access patterns to HA-SMR drives, so as to avoid the occurrences of long latencies in most cases and thus to ultimately improve the drive performance and responsiveness. We conduct experiments on real Seagate 8 TB HA-SMR drives to demonstrate the advantages of Virtual Persistent Cache over the real workloads from Microsoft Research Cambridge. The results show that the proposed design can remedy most of the long latencies and improve the drive performance by at least 58.11 percent, under the evaluated workloads.

Original languageEnglish (US)
Article number8387485
Pages (from-to)111-124
Number of pages14
JournalIEEE Transactions on Computers
Volume68
Issue number1
DOIs
StatePublished - Jan 1 2019

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Magnetic recording
Latency
Cache
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Design
Experiments

Keywords

  • Host-aware
  • long latency behavior
  • persistent cache
  • shingled magnetic recording (SMR)

Cite this

On Improving the Write Responsiveness for Host-Aware SMR Drives. / Yang, Ming Chang; Chang, Yuan Hao; Wu, Fenggang; Kuo, Tei Wei; Du, David H.

In: IEEE Transactions on Computers, Vol. 68, No. 1, 8387485, 01.01.2019, p. 111-124.

Research output: Contribution to journalArticle

Yang, Ming Chang ; Chang, Yuan Hao ; Wu, Fenggang ; Kuo, Tei Wei ; Du, David H. / On Improving the Write Responsiveness for Host-Aware SMR Drives. In: IEEE Transactions on Computers. 2019 ; Vol. 68, No. 1. pp. 111-124.
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