Abstract
Processing in memory (PiM) represents a promising computing paradigm to enhance performance of numerous dataintensive applications. Variants performing computing directly in emerging nonvolatile memories can deliver very high energy efficiency. PiM architectures directly inherit the vulnerabilities of the underlying memory substrates, but they also are subject to errors due to the computation in place. Numerous well-established error correcting codes (ECC) for memory exist, and are also considered in the PiM context, however, they typically ignore errors that occur throughout computation. In this paper we revisit the error correction design space for nonvolatile PiM, considering both storage/memory and computation-induced errors, surveying several self-checking and homomorphic approaches. We propose several solutions and analyze their complex performance-area-coverage trade-off, using three representative nonvolatile PiM technologies. All of these solutions guarantee single error correction for both, bulk bitwise computations and ordinary memory/storage errors.
Original language | English (US) |
---|---|
Title of host publication | Proceeding - 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture, ISCA 2024 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 678-692 |
Number of pages | 15 |
ISBN (Electronic) | 9798350326581 |
DOIs | |
State | Published - 2024 |
Event | 51st ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2024 - Buenos Aires, Argentina Duration: Jun 29 2024 → Jul 3 2024 |
Publication series
Name | Proceedings - International Symposium on Computer Architecture |
---|---|
ISSN (Print) | 1063-6897 |
ISSN (Electronic) | 2575-713X |
Conference
Conference | 51st ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2024 |
---|---|
Country/Territory | Argentina |
City | Buenos Aires |
Period | 6/29/24 → 7/3/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.