On-chip sparse learning with resistive cross-point array architecture

Shimeng Yu, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations


Unsupervised learning with sparse coding is widely adopted in applications of feature extraction, pattern classification, and compressive sensing. However, even with the state-of-the-art hardware platform of CPUs/GPUs, solving a sparse coding problem is still expensive in computation. In this paper, the resistive cross-point array architecture (CPA) is proposed to achieve on-chip acceleration of sparse coding, especially the matrix/vector operations that are intensively used in the algorithm. Learning and recognition experiments are conducted with the MNIST handwriting dataset. By co-optimizing the algorithm, architecture, circuit, and resistive synaptic devices, SPICE simulation at 65nm demonstrates that the CPA is able to accelerate sparse coding computation by more than 3800X, compared to software running on an 8-core CPU. Furthermore, this work investigates the technological limitations of a realistic resistive CPA, including reduced ON/OFF range of synaptic devices, nonlinearity in programming, spatial and temporal variations, and interconnect parasitics. The results illustrate both enormous opportunities and practical barriers of resistive CPA in real-time learning on a chip.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2015 - 25th 2015 Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery
Number of pages3
ISBN (Electronic)9781450334747
StatePublished - May 20 2015
Externally publishedYes
Event25th Great Lakes Symposium on VLSI, GLSVLSI 2015 - Pittsburgh, United States
Duration: May 20 2015May 22 2015

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI


Other25th Great Lakes Symposium on VLSI, GLSVLSI 2015
Country/TerritoryUnited States

Bibliographical note

Publisher Copyright:
Copyright © 2015 ACM.


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