On-Chip Sparse Learning Acceleration With CMOS and Resistive Synaptic Devices

Keyphrases

• On chip 100%
• Sparse Coding 100%
• Sparse Learning 100%
• Synaptic Device 100%
• Learning Acceleration 100%
• Parallel Architecture 60%
• Application Specific Integrated Circuits 60%
• Cross-point Array 60%
• Dictionary 40%
• Circuit Architecture 40%
• Hardware Accelerator 40%
• Performance Improvement 20%
• Signal Processing 20%
• Energy Efficient 20%
• Digital Circuits 20%
• Large-scale Learning 20%
• Learning Algorithm 20%
• Parallelization 20%
• Recent Advances 20%
• All-digital 20%
• Single chip 20%
• Object Recognition 20%
• Data Matrix 20%
• Coding Problems 20%
• Hardware Platform 20%
• Parallel Operation 20%
• Sequential Operation 20%
• Pattern Classification 20%
• Evolutionary Design 20%
• Matrix-vector multiplication 20%
• Learning Application 20%
• CPU-GPU 20%
• Data Fetching 20%
• Computing Unit 20%
• Resistive Random Access Memory (ReRAM) 20%
• Simulated Power 20%
• Read Circuit 20%
• Write Circuit 20%
• Von Neumann Architecture 20%
• Classification Recognition 20%
• Challenging Problems 20%
• Algorithm Architecture 20%
• Processing Patterns 20%

Computer Science

• Parallel Architectures 100%
• Application Specific Integrated Circuit 100%
• hardware acceleration 66%
• Object Recognition 33%
• Energy Efficient 33%
• Parallelization 33%
• Digital Circuit 33%
• Pattern Classification 33%
• Hardware Platform 33%
• Parallel Operation 33%
• Running Software 33%
• Vector Multiplication 33%
• Computing Units 33%
• Von Neumann Architecture 33%
• single-chip 33%
• Learning Algorithm 33%